Circuit Design for Testing Standard Cell Libraries

This work presents the design methodology and the architecture of simple, efficient and easy-to-use test circuits for evaluating and validating any set of library cells (combinational and sequential logic gates), both in the design environment and for on silicon prototyping. Evaluation and validation are accomplished considering functionality, performance, power consumption and impact in operation of nanometer aging effects. Simulation results demonstrate the behavior of the proposed design and the many facilities it provides.